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TMS320C5515
www.ti.com
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
Table 5-39. Switching Characteristics Over Recommended Operating Conditions for I2S Output
[I/O = 1.8 V] (see Figure 5-30 )
MASTER
SLAVE
NO.
PARAMETER
CV DD = 1.05 V
CV DD = 1.3 V
CV DD = 1.05 V
CV DD = 1.3 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1
2
3
t c(CLK)
t w(CLKH)
t w(CLKL)
t w(CLKL)
t w(CLKH)
Cycle time, I2S_CLK
Pulse duration, I2S_CLK high (CLKPOL = 0)
Pulse duration, I2S_CLK low (CLKPOL = 1)
Pulse duration, I2S_CLK low (CLKPOL = 0)
Pulse duration, I2S_CLK high (CLKPOL = 1)
50 or
2P (1) (2)
25
25
25
25
40 or
2P (1) (2)
20
20
20
20
50 or
2P (1) (2)
25
25
25
25
40 or
2P (1) (2)
20
20
20
20
ns
ns
ns
ns
ns
4
5
t dmax(CLKL-DXV)
t dmax(CLKH-DXV)
t dmax(CLKL-FSV)
t dmax(CLKH-FSV)
Output Delay time, I2S_CLK low to I2S_DX valid (CLKPOL = 0)
Output Delay time, I2S_CLK high to I2S_DX valid (CLKPOL = 1)
Delay time, I2S_CLK low to I2S_FS valid (CLKPOL = 0)
Delay time, I2S_CLK high to I2S_FS valid (CLKPOL = 1)
0
0
-1.1
-1.1
19
19
14
14
0
0
-1.1
-1.1
14
14
14
14
0
0
19
19
–
–
0
0
16.5
16.5
–
–
ns
ns
ns
ns
(1)
(2)
P = SYSCLK period in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.
Use whichever value is greater.
Copyright ? 2010–2013, Texas Instruments Incorporated
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